The present invention relates to a semiconductor device, and, more particularly, to a semiconductor device on which a logic circuit and a macro circuit, such as a macro memory that consumes more power than the logic circuit, are both mounted.
FIG. 1 is a schematic block diagram of a semiconductor device 100 on which a macro memory circuit 1 and a logic circuit 2 are both mounted. A common external power supply voltage is supplied to the memory circuit 1 and the logic circuit 2.
The memory circuit 1 comprises a plurality of internal power supply generation circuits which generate a plurality of different internal power supply voltages. FIG. 2 is a schematic circuit diagram of a substrate potential generation circuit 3 which is one of the plurality of internal power supply generation circuits.
The substrate potential generation circuit 3 includes a substrate potential detection circuit 4, an oscillator circuit 5 and a pump circuit 6. The substrate potential detection circuit 4 includes a P-channel MOS transistor Tr1 having a source connected to a high potential power supply Vcc via a resistor R1 and a drain connected to a low potential power supply Vss. A substrate potential VBB is supplied to the gate of the transistor Tr1 and the source (a node N1) of the transistor Tr1 is connected to the input terminal of an inverter circuit 7a. The output signal of the inverter circuit 7a is supplied to the oscillator circuit 5 via an inverter circuit 7b. 
In the substrate potential detection circuit 4, the drain current of the transistor Tr1 decreases along with an increase of the substrate potential VBB, and the potential of the node N1 increases along with a decrease of the drain current. If the potential of the node N1 is equal to or lower than the threshold of the inverter circuit 7a, the inverter circuit 7b outputs a signal having the L level. When the potential of the node N1 exceeds the threshold of the inverter circuit 7a, the inverter circuit 7b outputs a signal having the H level.
The output signal of the substrate potential detection circuit 4 is supplied to a NAND circuit 8a and the output signal of the NAND circuit 8a is supplied to the pump circuit 6 via an even number of inverter circuits 7c. The output signal of the inverter circuit 7c is also supplied to the NAND circuit 8a. 
In the oscillator circuit 5, if the output signal of the substrate potential detection circuit 4 is low, the output signal of the inverter circuit 7c is maintained at the H level. When the output signal of the substrate potential detection circuit 4 goes high, the oscillator circuit 5 generates an oscillation signal having a predetermined frequency in accordance with the delay times of the NAND circuit 8a and the inverter circuit 7c. 
The pump circuit 6 includes a capacitor 9 having an input terminal which receives the output signal of the oscillator circuit 5 and an output terminal connected to the anode of a diode 10a and the cathode of a diode 10b. The cathode of the diode 10a is connected to the low potential power supply Vss and the substrate potential VBB is input to the anode of the diode 10b. 
In the pump circuit 6, the potential of the input terminal of the capacitor 9 rises and falls in accordance with the oscillation signal output from the oscillator circuit 5 and the potential of the output terminal of the capacitor 9 rises and falls due to the capacitive coupling of the capacitor 9. The substrate potential VBB decreases due to the rising and falling operation.
In the substrate potential generation circuit 3, direct current (D.C.) is consumed when a drain current flows in the transistor Tr1 of the substrate potential detection circuit 4. Accordingly, the current consumption of the memory circuit 1 comprising a plurality of substrate potential generation circuits 3 is higher than that of the logic circuit 2. Thus, the normal operation of an internal power supply generation circuit such as the substrate potential generation circuit 3 increases the current consumption of the entire semiconductor device 100. Further, when the memory circuit 1 operates normally, whether the operating current of the logic circuit 2 is normal cannot be tested.
To reduce power consumption, the supply of the power to the memory circuit 1 should be cut off when the memory circuit 1 is not used. However, if a power supply voltage is supplied to the memory circuit 1 and the logic circuit 2 via a common power line, the power cannot be cut off only for the memory circuit 1.
If a power supply voltage is supplied separately to the memory circuit 1 and the logic circuit 2, only the power for the memory circuit 1 can be cut off. In this case, however, a malfunction such as hang-up operation or latch-up operation occurs due to the power supply potential difference when the power is cut off, causing the operation to become unstable.
An object of the present invention is to provide a semiconductor device which operates stably and has reduced power consumption.
In one aspect of the present invention, a semiconductor device includes a logic circuit and a macro circuit including a circuit that consumes direct current and stops operation in response to a stop signal.
A first switching circuit may be applied to the direct current consumption circuit. The first switch cuts off the direct current flowing in the direct current consumption circuit in response to the stop signal.
The macro circuit may include a data transfer circuit for generating a transfer data signal from an input data signal in accordance with a clock signal. A first reset circuit is connected to the data transfer circuit to reset the transfer data signal of the data transfer circuit in response to a reset signal. A power-on reset circuit is connected to the first reset circuit to generate the reset signal when power is provided thereto. A start signal generation circuit generates a start signal when the stop signal is deactivated. A second reset circuit is connected to the start signal generation circuit and the data transfer circuit to reset the transfer data signal in response to the start signal.
The macro circuit may include a data transfer circuit for generating a transfer data signal from an input data signal in accordance with a clock signal. A power-on reset circuit generates a reset signal when power is provided thereto. A start signal generation circuit generates a start signal when the stop signal is deactivated. A composite circuit is connected to the power-on reset circuit and the start signal generation circuit to generate a composite reset signal by combining the start signal and the reset signal. A reset circuit is connected to the composite circuit to reset the transfer data signal in response to the composite reset signal.
The macro circuit includes a data transfer circuit for generating a transfer data signal from an input data signal in accordance with a clock signal. A power-on reset circuit generates a reset signal when power is provided thereto. A composite circuit is connected to the power-on reset circuit to generate a composite reset signal by combining the stop signal and the reset signal. A reset circuit is connected to the composite circuit to reset the transfer data signal in response to the composite reset signal.